1. Field of the Invention
The present invention relates to semiconductor memory devices. More particularly, the invention relates to NOR flash memory and a related read method.
This application claims priority under 35 U.S.C § 119 to Korean Patent Application 2006-06870 filed on Jan. 23, 2006, the subject matter of which is hereby incorporated by reference.
2. Discussion of Related Art
Semiconductor memory devices are used in an increasing range of host devices to store data. Semiconductor memory devices are roughly categorized into a random access memory (RAM) and a read only memory (ROM). RAM is volatile in nature in that stored data is lost when power is interrupted. RAM includes dynamic RAM, static RAM, and the like. In contrast, ROM is nonvolatile in nature and stored data is retained following interruption of applied power. ROM includes programmable ROM (PROM), erasable PROM (EPROM), electrically EPROM (EEPROM) including flash memory, and the like.
Flash memory may be further classified as NAND flash memory and NOR flash memory. NAND flash memory is characterized by a string of series connected memory cells connected to a bit line, while NOR flash memory is characterized by memory cells connected in parallel with a bit line.
FIG. 1A shows a cross-section view of a memory cell in a NOR flash memory. FIG. 1B shows an equivalent circuit for the memory cell illustrated in FIG. 1A and its bias condition during a read operation.
Referring to FIG. 1A, a memory cell 10 includes a source 3, a drain 4, a first insulating film 5, a floating gate 6, a second insulating film 7, a control gate 8, and a substrate 9. The source 3 and drain 4 are formed on the p-type substrate 9.
The source 3 is connected to a source line SL, and drain 4 is connected to a bit line BL. Floating gate 6 is formed over and separated from a channel region by first insulating film 5 having a thickness (e.g.,) below about 100 nm. Control gate 8 is formed over and separated from floating gate 6 by second insulating film 7 (e.g., an ONO film). Control gate 8 is connected to a word line WL. Substrate 9 is biased with a bulk voltage BK.
The source 3, drain 4, control gate 8, and substrate 9 of memory cell 10 are supplied respectively with control voltages defined in relation to program/erase/read operations.
Referring to FIG. 1B, during a read operation, the source 3 receives a source line voltage of about 0V, drain 4 receives a bit line voltage of about 1V, and control gate 8 receives a word line voltage of about 5V. During the read operation, a bulk voltage of about 0V is applied to substrate 9.
If a read operation is carried out under the above-described bias conditions, and assuming the exemplary memory cell is being programmed, it may be seen that the current path between drain 4 and source 3 is cut-off. On the other hand, during an erase operation, the current path persists between drain 4 and source 3. Using conventional terminology, the programmed memory cell is said to be “OFF”, while the erased memory cell is said to be “ON”.
In general, NOR flash memories include a sense amplifier and an output driver adapted to read data from the memory cell during a read operation. The sense amplifier senses data stored in each memory cell, and the output driver develops output signals based on the sensed data capable of being exported to a host device or some other external circuit.
Both sense amplifier and output driver may be respectively supplied with a power supply voltage Vcc and a ground voltage Vss through a power terminal and a ground terminal. The output driver receives the power supply voltage Vcc or the ground voltage Vss and outputs sensed data in synchronization with a clock signal CLK. In general, the output driver may output 1-byte or 1-word data every clock cycle.
However, the sense amplifier performs its sense operation regardless of the clock signal (asynchronously). Since a conventional NOR flash memory performs sense operations asynchronously in relation to the clock signal CLK, sense operation failures may arise. Sense operation failure will be more fully described hereafter with reference to FIG. 3.
However, it should be noted at this point that as the output driver outputs data, it may also generate noise. Power supply or ground related noise generated by the output driver may corrupt the power supply voltage Vcc or a ground voltage Vss applied to the sense amplifier. The presence of noise on the power supply voltage Vcc or ground voltage Vss may actually result in sense operation failures in the conventional NOR flash memory.